Design IP can be used to overcome the productivity gap and time-to-market pressure in SoC design cycle. We built a high level of expertise in Digital ASIC Intellectual Property development. JBTechINDIA has comprehensive experience in all aspects of project development including definition, architecture design, algorithm development, RTL coding, verification, synthesis, FPGA implementation and testing. JBTechINDIA offers different products and turnkey solutions in the Digital Design IP Core domain such as video processing IPs, peripheral IPs, memory interface IPs, and bus protocol IPs, which can be easily integrated with any third party IP and SOC platform to reduce the development time. The design entry of these Semiconductor IP cores is done in Verilog HDL. These are fully synthesized IP cores, designed to be optimal in terms of power, speed and area and are tested.
SEMICONDUCTOR LOGIC DESIGN Logic, System and Circuit Design using Verilog and VHDL Timing Analysis Timing Backannotation to Netlist Static timing analysis Equivalency checking Design-for-test Scan insertion Complete to tape out and post routing Target devices: Digital ASICs (Application Specific ICs) Programmable Logic Design Gate Arrays FPGAs PALs Design, Synthesis Verification Programming Machine Language Coding Assembler Language Coding